The US Court of Appeals for the Federal Circuit issued decisions in two separate inter partes reviews (IPRs), one involving a patent related to radio frequency communication systems and the other involving a patent related to multi-processor systems. Intel Corporation v. Qualcomm Incorporated, Case No. 20-1664 (Fed. Cir. Dec. 28, 2021) (Prost, Taranto, Hughes, JJ.); Intel Corporation v. Qualcomm Incorporated, Case Nos. 20-1828, -1867 (Fed. Cir. Dec. 28, 2021) (Prost, Taranto, Hughes, JJ). Based on issues of claim construction and obviousness, the Court affirmed in part and vacated in part the Patent Trial and Appeal Board’s (Board) decision in the radio frequency communication systems patent IPR and vacated the Board’s decision in the multi-processor systems patent IPR.
Radio Frequency Communication System Patent IPR (1664)
In the IPR related to the radio frequency communication systems patent, Intel proposed that the claim term “radio frequency input signal” should take its ordinary meaning of an input signal having a radio frequency. Qualcomm argued that a person of skill in the art reading the patent would understand the phrase to reference the radio frequency signal that is received before down-conversion, and thus proposed that the term should mean “a signal centered at a carrier frequency at which the signal was transmitted/received.” The Board agreed with Qualcomm based on the intrinsic evidence.
Intel argued before the Board that certain claims of the radio frequency communication systems patent would have been obvious in light of the Der reference and the Valla reference. Qualcomm argued that a skilled artisan would not have been motivated to combine Der and Valla, because Der’s transistor would defeat the intended purpose of Valla’s amplifier. The Board agreed with Qualcomm. Qualcomm also submitted substitute claims. The Board accepted the substitute claims after finding that a skilled artisan would have lacked reason to combine Der and the Burgener reference to achieve the substitute claims. Intel appealed.
The Federal Circuit first addressed the threshold question of whether it had jurisdiction since no lawsuit had been filed against Intel. Despite the absence of any lawsuit against Intel itself, the Court found that Intel had standing because it had engaged in acts that previously resulted in assertion of the patent against one of Intel’s customers. Because Intel continues to sell the relevant products to that customer and others, it must address the risk of an infringement suit by Qualcomm. Qualcomm also refused to offer a covenant not to sue or stipulate that it would not reassert its prior infringement allegations involving the Intel products. The Court found that this refusal made Intel’s risk more than “mere conjecture or hypothesis.” Therefore, the Court found that Intel had standing to pursue the appeal.
Turning to the merits, the Federal Circuit affirmed the Board’s construction of “radio frequency input signal.” The Court explained that while both parties’ proposed constructions had appeal when considered in a vacuum, the proper inquiry required analysis of the surrounding claim language and specification. The Court found that linguistic clues in the claims suggested that the claimed “radio frequency input signal” referred to the signal entering the device and not a signal simply entering any component within the device. The Court also found that this interpretation was consistent with the specification, which consistently used the term “radio frequency input signal” to reference the signal received at the device’s antenna before down conversion. The Court rejected Intel’s argument that the adopted construction limited the ordinary meaning to the patent’s embodiments, explaining that the adopted construction was contextually correct based on its usage in the intrinsic evidence.
Turning to the obviousness, Intel argued that the Board did not “apply the proper mode of legal analysis [of] weigh[ing] the putative disadvantage . . . against the combination’s undisputed benefits.” The Federal Circuit disagreed, finding that the Board weighed the competing evidence and concluded that a skilled artisan would have lacked motivation to combine Valla with Der because it “would impair Valla’s need for low impedance during the majority of operation (emphasis in original).” The Court noted that the parties’ respective experts did not disagree as to how the prior art would operate in the low impedance mode. The Court explained that the Board considered the relevant tradeoffs and concluded that based on the stated importance of low impedance as “key” to Valla, negating this benefit during the majority of operation would outweigh any reason to combine. The Court thus affirmed the nonobviousness finding.
Turning to the patentability of the substitute claims, the Federal Circuit concluded that substantial evidence did not support the Board’s determination that a skilled artisan would have lacked reason to combine Der with Burgener. The Court reexamined the prior art and explained that the Board erred in concluding that Burgener failed to provide sufficient motivation to a skilled artisan to select the prior art switch described in the background section of Burgener, which Burgener criticized for being less effective and purported to improvement. The Court noted that petitioner’s presentation of how the prior art would have been combined and why, “[f]ar from being conclusory, ‘fit the teachings of multiple patents together like pieces of a puzzle.’ The Board’s critique of this rationale as impermissibly ‘generic’ is not supported by substantial evidence.” The Court therefore vacated the Board’s decision as to the substitute claims and remanded for further consideration.
Multi-Processor Systems Patent IPR (1828; 1867)
In the IPR related to the multi-processor systems patent, Intel argued that the claim term “hardware buffer” should be given its ordinary meaning of “a buffer implemented in hardware.” Qualcomm argued that the “hardware buffer” was a permanent buffer within the hardware transport mechanism and did not include a temporary buffer in system memory. The Board agreed with Qualcomm and concluded that the claimed “hardware buffer” excluded temporary buffers. Relying on the negative claim construction, the Board rejected Intel’s challenge on obviousness as to certain claims over the Svensson reference because the disclosed “intermediate storage area” was a temporary buffer and thus different from the claimed “hardware buffer” (i.e., permanent buffers, excluding temporary buffers).
As to the other challenged claims containing means-plus-function limitations, the Board concluded that Intel failed to disclose sufficient structure corresponding to a “means for processing” and a “means for scatter loading,” and thus failed to show unpatentability since Intel did not meet its burden to show structure corresponding to the claimed function to which the Board could compare the prior art’s disclosure. Intel appealed.
As with the radio frequency communication systems patent IPR, the Federal Circuit first considered whether Intel had standing to appeal. The Court came to the same conclusion as it did in the above opinion, finding that Intel had standing to appeal because it engaged in activity that had already led to an infringement suit involving the same patent and component supplied by Intel.
Turning to the merits, the Federal Circuit rejected the Board’s construction of “hardware buffer” and remanded with instructions to adopt an affirmative claim construction in place of the Board’s purely negative construction. The Court noted that Intel’s definition of a “hardware buffer” being a “buffer implemented in hardware” would render the word “hardware” meaningless, because every buffer is ultimately implemented on a physical device (i.e., hardware). The Court further found that the Board failed to analyze the distinction between a “system memory” and a “hardware buffer,” both of which were recited in challenged claim. The Court also found that the Board fell short in analyzing the written description related to “hardware buffer” when adopting its construction. The Court criticized the Board’s takeaway from the discussion of “temporary” buffers in the specification: “The Board’s construction was entirely a negative one—excluding ‘temporary’ buffers. . . . It is not clear what precisely constitutes a ‘temporary buffer’ as recited in the Board’s construction. To resolve even that uncertainty requires the kind of additional, substantive understanding discussed above, which seems likely to support an affirmative construction in place of the Board’s purely negative one.” Since the Board relied its obviousness determination on its negative claim constructions of a “hardware buffer,” the Court remanded for reconsideration of the obviousness determination upon the proper claim construction of a “hardware buffer.”
The Federal Circuit also determined that the Board’s conclusion regarding the claims having means-plus-function limitations was error because the Board failed to decide for itself whether the specification provided sufficient corresponding structure for the means-plus-function limitations. The Court noted that while an IPR is statutorily intended to protect the interests “of the petitioner in securing a determination on the patentability of a claim,” it also “reflects a public interest in the Board’s answering the patentability questions.” Here, the Court found the Board’s acceptance of a party concession on corresponding structure improper: “The Board did not itself conclude that the prior-art analysis task was impossible, and it could not so conclude here without determining for itself that such structure was missing, a legal question that is part of claim construction.” The Court vacated and remanded for consideration of potential indefiniteness of the means-plus-function limitations.