The US Court of Appeals for the Federal Circuit, addressing the issue of whether certain factual and legal conclusions relating to obviousness were supported by substantial evidence, held that the Patent Trial & Appeal Board improperly rejected evidence of “known-technique” rationale to provide a motivation to combine. Intel Corp. v. PACT XPP Schweiz AG, Case No. 22-1037 (Fed. Cir. Mar. 13, 2023) (Newman, Prost, Hughes, JJ.)
PACT owns a patent that “relates to multiprocessor systems and how processors in those systems access data.” The claimed multiprocessor system addressed cache incoherency, a problem associated with the use of multiple cache memories to store data, particularly local copies of the same data stored on multiple processors. Cache incoherency (i.e., inconsistencies among different cache processors) “may arise if one processor changes its local copy of the data and that change isn’t propagated to the other copies of that data.”
Intel petitioned for inter partes review of claims 4 and 5 of the patent, relying on two prior art references, Kabemoto and Bauman. Kabemoto and Bauman both address the problem of cache incoherency. As the Federal Circuit explained, Kabemoto maintains cache coherency “by ‘snooping’ along a shared ‘bus,’” while Bauman “us[es] a global, segmented secondary cache.”
The Board upheld the patentability of the challenged claims, concluding that “Intel failed to prove the obviousness of each limitation of [independent] claim 4,” from which claim 5 depended. Intel had contended that a person of ordinary skill in the art would combine Kabemoto and Bauman to teach all limitations in claim 4 by “replac[ing] Kabemoto’s secondary caches” with “Bauman’s segmented global [secondary cache],” which is a separate cache. PACT did not dispute that the combination of Kabemoto and Bauman taught each limitation of claim 4 but argued that Intel failed to demonstrate a motivation to combine Kabemoto and Bauman.
The Board nevertheless found that Intel failed to demonstrate that the prior art disclosed the segment-to-segment limitation and concluded that Intel failed to show that a person of ordinary skill in the art would have been motivated to combine the teachings of Kabemoto and Bauman. Intel appealed.
The Federal Circuit first addressed Intel’s contention “that substantial evidence d[id] not support the Board’s determination that the prior art fails to disclose the segment-by-segment limitation” of claim 4. The Court found that “Bauman’s Figure 6 teaches—if not plainly illustrates—the segment-to-segment limitation of the claims interconnect system” and reversed the Board’s contrary conclusion.
Next, the Federal Circuit addressed Intel’s contention that the Board’s determination that there was no motivation to combine Kabemoto and Bauman was not supported by substantial evidence. On this issue, the Court reasoned that under KSR, it was “enough for Intel to show that there was a known problem of cache incoherency in the art, that Bauman’s secondary cache helped address that issue, and that combining the teachings of Kabemoto and Bauman wasn’t beyond the skill of an ordinary artisan.” As the Court put it, “[n]othing more is required to show a motivation to combine under KSR.”