Addressing claim construction issues in inter partes review (IPR) proceedings before the Patent Trial & Appeal Board (Board), the US Court of Appeals for the Federal Circuit affirmed an obviousness finding as to some claims but reversed and remanded an obviousness finding as to another claim because of a claim construction error. VLSI Technology LLC v. Intel Corporation, Case Nos. 21-1826, -1827, -1828 (Fed. Cir. Nov. 15, 2022) (Chen, Bryson, Hughes, JJ.)
VLSI owns a patent directed to a technique for alleviating the problems of defects caused by stress applied to bond pads of an integrated circuit. Bond pads are a portion of an integrated circuit that sit above interconnected circuit layers and are used to attach the chip to another electronic component, such as a computer or motherboard. When a chip is attached to another electronic component, forces are exerted on the chip’s bond pad, which can result in damage to the interconnect layers. The patent discloses improvements to the structures of an integrated circuit that reduce the potential for damage to the interconnect layers when the chip is attached to another electronic component while also permitting each of the layers underlying the pad to be functionally independent in the circuit.
VLSI filed suit against Intel alleging infringement of the patent. During claim construction, the district court construed the claim term “force region” to mean a “region within the integrated circuit in which forces are exerted on the interconnect structure when a die attach is performed.” Before the district court’s construction but after the suit was filed, Intel filed petitions for IPR of the patent and advocated in its petitions for the same construction of “force region” that the district court ultimately adopted.
VLSI did not contest Intel’s construction, but it later became apparent that the two parties disagreed over the meaning of “die attach,” which formed part of the construction. Intel argued that the term “die attach” refers to any method of attaching a chip to another electronic component, including a method known as wire bonding, which was taught by a prior art reference included in Intel’s petitions. VLSI argued that the term refers to a method of attachment known as “flip chip” bonding and does not include wire bonding. In the Board’s final written decisions, it did not address the term “die attach,” but found that “force region” was not limited to flip chip bonding and subsequently found the challenged claims invalid as obvious. The Board also construed a second disputed term “used for electrical interconnection not directly connected to the bond pad,” which is recited in only one claim of the patent, in favor of Intel, and subsequently found that claim unpatentable. VLSI appealed.
On appeal, VLSI raised a number of procedural and substantive challenges to the Board’s construction of the two disputed terms. VLSI argued that the Board failed to acknowledge and give appropriate weight to the district court’s construction of “force region.” The Federal Circuit dismissed this argument, as there was ample evidence in [...]